The present invention generally relates to semiconductor devices and more particularly to a high-frequency semiconductor device operable in the GHz band, as well as the art of mounting such a high-frequency semiconductor device on a substrate to form a monolithic microwave integrated circuit (MMIC).
In relation to portable information processing apparatuses and systems including a portable telephone system known as PHS (personal handy-phone system), and further in relation to the construction of a radio LAN (local-area network) system, there is an increasing demand for semiconductor devices operable in the GHz band.
Generally, the semiconductor devices for use in such millimeter wave or microwave applications are formed of a MESFET or a HEMT, or alternatively an HBT, wherein such active devices are integrated with passive devices such as an MIM (metal-insulator-metal) capacitor or a spiral inductance to form an MMIC, together with a high-frequency transmission line such as a microstrip line provided on a common substrate on which the MMIC is to be formed.
FIG. 1 shows the typical construction of a conventional, general purpose semiconductor device.
Referring to FIG. 1, the semiconductor device includes a substrate 6 formed of a Si slab or a glass slab on which a ground plane 2, a dielectric layer 3 and a transmission line 5 are formed, wherein the substrate 6 further carries thereon a semiconductor chip 1 in a face-up state. Thereby, the transmission line 5 forms, together with the ground plane 2 and the intervening dielectric layer 3, a microstrip line, and electrode pads formed on the top surface of the semiconductor chip 1 are connected to the microstrip line 5 by corresponding bonding wires 4.
When the construction of FIG. 1 is to be used for the MMIC or a similar device for GHz applications, there arises a problem, associated with the use of the bonding wires 4 for interconnection between the semiconductor chip 1 and the microstrip line 5, in that the microwave signals propagating through the bonding wires 4 may be reflected back and forth due to the parasitic inductance of the bonding wire 4. Thereby, there can be a serious loss of the microwave signals.
In order to avoid the problem of parasitic inductance of the bonding wires, there is proposed a flip-chip mounting process in which the semiconductor chip is mounted upon a mount substrate, on which a microstrip line is formed, in a facedown state such that the electrode pads on the semiconductor chip is connected to the microstrip line directly, with a minimum distance. This process is also called an MBB (micro bump bonding) process. According to the flip-chip process, the bonding wires are eliminated and the parasitic inductance between the semiconductor chip and the microstrip line on the mount substrate is minimized successfully.
FIGS. 2A and 2B show the construction of an MMIC formed by the flip-chip process as proposed in the Laid-Open Japanese Patent Publication 08-316368, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. It should be noted that FIG. 2A shows the MMIC in the state before the flip-chip mounting process while FIG. 2B shows the same MMIC in the state after the flip-chip mounting process.
Referring to FIG. 2A, the ground plane 2 may be the layer of an Al—Si—Cu alloy formed on the substrate 6 with a thickness of about 1 μm. On the other hand, the dielectric layer 3 may be formed of an SiO2 film having a thickness of about 20 μm. Further, the transmission line 5 may be formed of a layer of a conductive material such as Au formed with a thickness of typically 3-5 μm.
In the illustrated example, it should be noted that a bonding pad 51 is formed on the mount substrate 6 as a part of the transmission line 5, wherein the bonding pad 51 carries thereon a micro bump 53 for the MBB process of the semiconductor chip 1. In correspondence to the bonding pad 51, the semiconductor chip 1 carries, on the bottom surface thereof, a wiring pattern 9 and a bonding pad 52 corresponding to the bonding pad 51. It should be noted that the foregoing bottom surface of the semiconductor chip 1 is actually a top surface when the semiconductor chip 1 is in an ordinary, faceup state.
In the state of FIG. 2B, the foregoing semiconductor chip 1 is mounted upon the mount substrate 6 by the MBB process, wherein it should be noted that the bonding pad 51 of the microstrip line 5 and the corresponding bonding pad on the chip 1 are now connected with each other by the micro bump 53, and the micro bump 53 forms a rigid interconnection part 8. Typically, the micro bump 53 has a diameter of 10-20 μm and a height of several microns in the state of FIG. 2A before the mounting, while the micro bump 53 generally undergoes a lateral expansion in the state of FIG. 2B due to the mechanical deformation caused as a result of the mounting. As a result of such a mechanical deformation, the micro bump 53 typically has a diameter of several ten microns and a height of 1-2 μm in the state of FIG. 2B.
Thus, by using the flip-chip mounting process, the distance between the semiconductor chip 1 and the interconnection part 8 on the mount substrate 6 is reduced to 1-2 μm, and the problem of the parasitic inductance of the bonding wire as in the case of the construction of FIG. 1 is successfully eliminated.
On the other hand, there is a possibility in the flip-chip construction of FIGS. 2A and 2B in that the impedance of the wiring pattern 9 may be changed when the distance between the semiconductor chip 1 and the mount substrate 6 and hence the microstrip line 5, is reduced excessively as such. This problem may become particularly conspicuous in the case where there is provided a coplanar strip line on the bottom surface of the semiconductor chip 1 as the wiring pattern 9. In the case of a coplanar strip line, in which the electric field of the wiring pattern 9 is leaking toward the semiconductor chip 1, it is expected that the effect of the impedance change is more significant as compared with the case in which a microstrip line is formed on the semiconductor chip 1 as the wiring pattern 9.
It should be noted that a microstrip line conventionally formed on a semiconductor chip such as the semiconductor chip 1 for the wiring pattern 9 includes a ground plane provided on the rear surface (top surface in the illustrated state) of the semiconductor chip 1, and via holes are formed so as to penetrate through the semiconductor chip for connection to the ground plane. However, such a construction of the semiconductor chip 1 reduces the degree of freedom in designing the wiring pattern 9 substantially.
In the case of using a coplanar strip on the semiconductor chip 1, in which a ground pattern is provided adjacent to the wiring pattern used for carrying a high-frequency signal, it should be noted that such a construction requires an air bridge structure for interconnecting a pair of such ground patterns locating at both lateral sides of the wiring pattern at the part where the foregoing ground pattern pair form a single ground line intersecting the wiring pattern.
FIGS. 3A and 3B show an example of such an air bridge structure 7 respectively in a side view and a front view, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIGS. 3A and 3B, the air bridge structure 7 is formed of a conductor material such as Au and has a thickness of 2-4 μm and a width of 20-30 μm, wherein the air bridge structure 7 bridges over a space 30 having a height of typically 3-5 μm and extends typically over a length of 50-80 μm. Thereby, the total amount of projection y of the air bridge structure 7 as measured in the downward direction from the bottom surface of the semiconductor chip 1 in the state of FIG. 2B becomes 5-9 μm, wherein it should be noted that the projection y is given as a sum of the height x of the space 30 and the thickness of the conductor strip forming the air bridge structure 7.
FIG. 4 shows a structure that would be needed for mounting a semiconductor chip carrying thereon a tall air bridge structure, on a mount substrate in the facedown state, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 4, the semiconductor chip 1 carrying thereon the air bridge structure 7 is flip-chip mounted in the inverted state, wherein it should be noted that the construction of FIG. 4 requires a substantial height x for the interconnection part 8, so that the problem of the air bridge structure 7 abutting to the top surface of the dielectric layer 3 is avoided. This, however, means that it is necessary to set the height x of the interconnection part 8 or micro bump to be comparable to or larger than the foregoing downward protrusion y of the air bridge structure 7, while such a construction increases the parasitic inductance of the interconnection part 8 and the advantageous feature of the flip-chip mounting process is lost substantially. Further, such a construction is unstable when the interconnection part 8 is to be formed by a solder bump.
Further, the foregoing conventional flip-chip construction of FIGS. 2A and 2B or FIG. 4 requires a high-precision positioning of the semiconductor chip 1 relative to the mount substrate 6, and it has been necessary to use an expensive alignment apparatus for the fabrication of the semiconductor device.